频率计实验报告

基于FPGA的数字频率计实验报告

1．实验要求

(1) 目的：掌握FPGA设计流程和VHDL；掌握频率计原理及其FPGA的实现方法。 (2) 实验设备：PC机、Quartus II软件、DE2开发板。 (3) 实验内容及要求： ① 频率和周期测量

信号：脉冲波；频率：1Hz～100KHz（由DE2上 27/50 MHz时钟分频得到） ② 测量方式

连续；单次/连续双重方式(选做) ③可5S自动刷新，也可以手动控制刷新 ④显示 2.设计流程图

3．顶层逻辑框图

pin_namePIN_N2INPUTVCCPIN_AE14PIN_AF14PIN_AD13pin0pin1pin2clkwINPUTVCCINPUTVCCINPUTVCCINPUTVCCfenpingclkpin0pin1pin2clkwinst1clkoutxuanzezhoupinclk1clkbianchoosestartINPUTVCCliuweijiafabclkclkenrled0[7..1]led1[7..1]led2[7..1]led3[7..1]led4[7..1]led5[7..1]OUTPUTOUTPUTOUTPUTOUTPUTclk1clkenrenchoosepin_name11[7..1]pin_name12[7..1]pin_name13[7..1]pin_name14[7..1]pin_name15[7..1]pin_name16[7..1]OUTPUTOUTPUTinst5inst3PIN_N25shoudonginst2PIN_N26zidongpinzhouINPUTVCCINPUTVCCPIN_V13PIN_V14PIN_AB24PIN_AD11PIN_AA23PIN_Y24PIN_AE11PIN_AA24PIN_AB25PIN_W24PIN_AC12PIN_Y22PIN_AB26PIN_U22PIN_T3PIN_AB12PIN_W21PIN_AC26PIN_Y25PIN_R6PIN_R3PIN_AF10PIN_V21PIN_AC25PIN_Y26PIN_R7PIN_R4PIN_V20PIN_V22PIN_AA26PIN_T4PIN_R5PIN_AB23PIN_AA25PIN_U2PIN_T9PIN_Y23PIN_U1PIN_P7PIN_U9PIN_P6PIN_T2PIN_P25

4．附录（源程序代码） 分频模块

library ieee;

USE IEEE.STD_LOGIC_11.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY fenping IS

PORT(clk,pin0,pin1,pin2,clkw:IN STD_LOGIC; clkout:out STD_LOGIC); END fenping;

ARCHITECTURE a OF fenping is signal clk1:std_logic; signal clk2:std_logic; signal clk3:std_logic; signal clk4:std_logic; begin

process(clk)

variable m0:integer range 0 to 4999; variable m1:integer range 0 to 24999; variable m2:integer range 0 to 49999; variable m3:integer range 0 to 99999; begin

if clk'event and clk='1' then if m0<=2499 then m0:=m0+1; clk1<='0';

elsif m0=4999 then m0:=0;

clk1<='1'; else

m0:=m0+1; clk1<='1'; end if;

if m1<=12499 then m1:=m1+1;

clk2<='0';

elsif m1=24999 then m1:=0; clk2<='1'; else m1:=m1+1; clk2<='1'; end if;

if m2<=24999 then m2:=m2+1; clk3<='0';

elsif m2=49999 then

--10k时钟 --2k时钟 --1k时钟 --500hz时钟

m2:=0; clk3<='1'; else

m2:=m2+1; clk3<='1'; end if;

if m3<=49999 then m3:=m3+1;

clk4<='0';

elsif m3=99999 then m3:=0; clk4<='1'; else

m3:=m3+1;

clk4<='1'; end if; end if;

if(pin2='0' and pin1='0' and pin0='0') then clkout<=clk1;

elsif(pin2='0' and pin1='0' and pin0='1') then clkout<=clk2;

elsif(pin2='0' and pin1='1' and pin0='0') then clkout<=clk3;

elsif(pin2='0' and pin1='1' and pin0='1') then clkout<=clk4; else

clkout<=clkw; end if;

end process; end a;

频周计数时钟产生模块 LIBRARY IEEE;

USE IEEE.STD_LOGIC_11.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY zhoupin IS

PORT(clk1,clk,bian,choose,start:IN STD_LOGIC; en,r:buffer STD_LOGIC); END zhoupin;

ARCHITECTURE a OF zhoupin IS

signal q :integer range 0 to 11;

signal q0 :integer range 0 to 49999999; signal s,r0:std_logic; begin

process(clk)

variable m:integer range 0 to 249999999; begin

if clk'event and clk='1' then --5S时钟脉冲用来控制自动刷新 if m<249999999 then m:=m+1; s<='0';

elsif m=249999999 then m:=0; s<='1'; end if; end if; end process; process(clk) begin

if bian='1' then r<=s; --bian=1 时5s自动刷新 else r<=start; --bian=0 时start控制 end if;

end process;

process(clk1) begin

if choose='1' then -- choose=1 测周时钟 if r='1' then q<=0; elsif clk1'event and clk1='1' then if q<11 then q<=q+1; else q<=11;

end if; end if;

if q<11 and q/=0 then en<='1'; else en<='0'; end if;

else -- choose=0测频时钟 if r='1' then q0<=0;

elsif clk'event and clk='1' then

if q0<49999999 then q0<=q0+1; else q0<=49999999; end if; end if;

if q0<49999999 and r='0' then en<='1'; else en<='0'; end if; end if; end process; end a;

频周计数时钟选择模块

LIBRARY IEEE;

USE IEEE.STD_LOGIC_11.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY xuanze IS

PORT(clk1,clk,en,choose:IN STD_LOGIC; bclk:out STD_LOGIC); END xuanze;

ARCHITECTURE a OF xuanze IS signal p:std_logic; BEGIN

process(en,clk1,p,clk) begin

if choose='1' then bclk<=p and en; else bclk<=clk1 and en; end if;

end process; process(clk)

variable n:integer range 0 to 499; begin

if clk'event and clk='1' then --产生100khz时钟 if n<=249 then n:=n+1; p<='0';

elsif n=499 then n:=0; p<='1'; else n:=n+1; p<='1'; end if; end if; end process; end a;

6位十进制计数模块 LIBRARY IEEE;

USE IEEE.STD_LOGIC_11.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY liuweijiafa IS

PORT(clk,en,r:IN STD_LOGIC;

led0,led1,led2,led3,led4,led5:OUT STD_LOGIC_VECTOR(7 DOWNTO 1)); END liuweijiafa;

ARCHITECTURE a OF liuweijiafa IS

SIGNAL b1,b2,b3,b4,b5,b6:STD_LOGIC_VECTOR(3 DOWNTO 0);

BEGIN

p1:PROCESS(clk) BEGIN

if r='1' then --清零

b1<=\"0000\";b2<=\"0000\";b3<=\"0000\";b4<=\"0000\";b5<=\"0000\";b6<=\"0000\"; elsif bclk'event and bclk='1' then

if b1=\"1001\" then b1<=\"0000\"; --个位十进制计数 if b2=\"1001\" then b2<=\"0000\"; --百位十进制计数 if b3=\"1001\" then b3<=\"0000\"; --千位十进制计数 if b4=\"1001\" then b4<=\"0000\"; if b5=\"1001\" THEN b5<=\"0000\"; if b6=\"1001\" then b6<=\"0000\"; else b6<=b6+1; end if; else b5<=b5+1; end if;

else b4<=b4+1; end if; else b3<=b3+1; end if;

else b2<=b2+1; end if; else b1<=b1+1; end if; end if;

end process;

m0: process (clk) begin if en='0' then case b1 is

when \"0000\"=>led0(7 downto 1)<=\"1000000\"; when \"0001\"=>led0(7 downto 1)<=\"1111001\"; when \"0010\"=>led0(7 downto 1)<=\"0100100\"; when \"0011\"=>led0(7 downto 1)<=\"0110000\"; when \"0100\"=>led0(7 downto 1)<=\"0011001\"; when \"0101\"=>led0(7 downto 1)<=\"0010010\"; when \"0110\"=>led0(7 downto 1)<=\"0000010\"; when \"0111\"=>led0(7 downto 1)<=\"1111000\"; when \"1000\"=>led0(7 downto 1)<=\"0000000\"; when \"1001\"=>led0(7 downto 1)<=\"0010000\"; when others=>led0(7 downto 1)<=\"1111111\"; end case; case b2 is

when \"0000\"=>led1(7 downto 1)<=\"1000000\";

--万位十进制计数 --十万位十进制计数 --百万位十进制计数 --7段译码的0译码 --7段译码的1译码 --7段译码的2译码 --7段译码的3译码 --7段译码的4译码 --7段译码的5译码 --7段译码的6译码 --7段译码的7译码 --7段译码的8译码 --7段译码的9译码 --7段译码的1译码无显示

when \"0001\"=>led1(7 downto 1)<=\"1111001\"; when \"0010\"=>led1(7 downto 1)<=\"0100100\"; when \"0011\"=>led1(7 downto 1)<=\"0110000\"; when \"0100\"=>led1(7 downto 1)<=\"0011001\"; when \"0101\"=>led1(7 downto 1)<=\"0010010\"; when \"0110\"=>led1(7 downto 1)<=\"0000010\"; when \"0111\"=>led1(7 downto 1)<=\"1111000\"; when \"1000\"=>led1(7 downto 1)<=\"0000000\"; when \"1001\"=>led1(7 downto 1)<=\"0010000\"; when others=>led1(7 downto 1)<=\"1111111\"; end case; case b3 is

when \"0000\"=>led2(7 downto 1)<=\"1000000\"; when \"0001\"=>led2(7 downto 1)<=\"1111001\"; when \"0010\"=>led2(7 downto 1)<=\"0100100\"; when \"0011\"=>led2(7 downto 1)<=\"0110000\"; when \"0100\"=>led2(7 downto 1)<=\"0011001\"; when \"0101\"=>led2(7 downto 1)<=\"0010010\"; when \"0110\"=>led2(7 downto 1)<=\"0000010\"; when \"0111\"=>led2(7 downto 1)<=\"1111000\"; when \"1000\"=>led2(7 downto 1)<=\"0000000\"; when \"1001\"=>led2(7 downto 1)<=\"0010000\"; when others=>led2(7 downto 1)<=\"1111111\"; end case; case b4 is

when \"0000\"=>led3(7 downto 1)<=\"1000000\"; when \"0001\"=>led3(7 downto 1)<=\"1111001\"; when \"0010\"=>led3(7 downto 1)<=\"0100100\"; when \"0011\"=>led3(7 downto 1)<=\"0110000\"; when \"0100\"=>led3(7 downto 1)<=\"0011001\"; when \"0101\"=>led3(7 downto 1)<=\"0010010\"; when \"0110\"=>led3(7 downto 1)<=\"0000010\"; when \"0111\"=>led3(7 downto 1)<=\"1111000\"; when \"1000\"=>led3(7 downto 1)<=\"0000000\"; when \"1001\"=>led3(7 downto 1)<=\"0010000\"; when others=>led3(7 downto 1)<=\"1111111\"; end case;

case b5 is

when \"0000\"=>led4(7 downto 1)<=\"1000000\"; when \"0001\"=>led4(7 downto 1)<=\"1111001\"; when \"0010\"=>led4(7 downto 1)<=\"0100100\"; when \"0011\"=>led4(7 downto 1)<=\"0110000\"; when \"0100\"=>led4(7 downto 1)<=\"0011001\"; when \"0101\"=>led4(7 downto 1)<=\"0010010\";

when \"0110\"=>led4(7 downto 1)<=\"0000010\"; when \"0111\"=>led4(7 downto 1)<=\"1111000\"; when \"1000\"=>led4(7 downto 1)<=\"0000000\"; when \"1001\"=>led4(7 downto 1)<=\"0010000\"; when others=>led4(7 downto 1)<=\"1111111\"; end case; case b6 is

when \"0000\"=>led5(7 downto 1)<=\"1000000\"; when \"0001\"=>led5(7 downto 1)<=\"1111001\"; when \"0010\"=>led5(7 downto 1)<=\"0100100\"; when \"0011\"=>led5(7 downto 1)<=\"0110000\"; when \"0100\"=>led5(7 downto 1)<=\"0011001\"; when \"0101\"=>led5(7 downto 1)<=\"0010010\"; when \"0110\"=>led5(7 downto 1)<=\"0000010\"; when \"0111\"=>led5(7 downto 1)<=\"1111000\"; when \"1000\"=>led5(7 downto 1)<=\"0000000\"; when \"1001\"=>led5(7 downto 1)<=\"0010000\"; when others=>led5(7 downto 1)<=\"1111111\"; end case; end if;

end process; END a;